//  Copyright (c) 2010 by Dolphin Technology
//  All rights rerved.
//
//  Copyright Notification
//  No part may be reproduced except as authorized by written permission.
// 
//% @file   dti_shftreg_tb.v
//% @par    Company:
//%             Dolphin Technology 
//% @par    Project:
//%             [projectname]
//% @par    Author:
//%             N. Huy Bui
//% @par    Date:
//%             July 9, 2012
//% @brief
//%             testbench for [dti_shftreg] module
//$Id$

module dti_shftreg_tb;
parameter 	  LENGTH      = 5;
reg 		  clk_tb;
reg 		  load_n_tb;
reg 		  shift_n_tb;
reg 		  s_in_tb;
reg 	  [LENGTH-1:0] p_in_tb;

wire 	  [LENGTH-1:0] p_out_tb;

initial 
begin
  clk_tb = 0;
  load_n_tb = 0;
  shift_n_tb = 1;
  s_in_tb = 0;
  p_in_tb = 5'b00001;
  #12 load_n_tb = 1;
  #10 shift_n_tb = 0;
  #50 p_in_tb = 5'b00011;
  #10 load_n_tb = 0;
  #15 load_n_tb = 1;
  #20 shift_n_tb = 1;
  #20 $finish;
end

always #5 clk_tb = ~clk_tb;

dti_shftreg DUT (
  .clk 		(clk_tb),
  .load_n 	(load_n_tb),
  .shift_n 	(shift_n_tb),
  .s_in 	(s_in_tb),
  .p_in 	(p_in_tb),
  .p_out 	(p_out_tb));

endmodule // dti_shftreg_tb
